`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/02/05 23:02:59
// Design Name:
// Module Name: mem_data
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module mem_data(input clk,
                input [31:0] number_value,
                output reg [31:0] addr = 0,
                output reg en = 1,
                output reg rst = 0,
                output reg [3:0] we = 0,
                output reg [31:0] data = 0,
                output reg data_done = 0);
    
    reg [2:0] rom_state     = 0;
    reg [15:0] test_time    = 0;
    reg [7:0] delay_counter = 0;
    
    reg [31:0] counter = 0;
    
    reg start_sig = 0;
    
    always @(posedge clk) begin
        
        if (counter < number_value-1) begin
            counter   <= counter + 1;
            start_sig <= 0;
        end
        else begin
            counter   <= 0;
            start_sig <= 1;
        end
        
        case (rom_state)
            0 : begin
                if (start_sig) begin
                    rom_state <= 1;
                    test_time <= test_time + 1;
                end
                data <= test_time;
            end
            1 : begin
                
                if (addr<4095-4) begin
                    we   <= 4'b1111;
                    addr <= addr + 4;
                    data <= data + 1;
                end
                else begin
                    addr      <= 0;
                    we        <= 4'b0000;
                    rom_state <= 2;
                end
            end
            2 : begin
                if (delay_counter<20) begin
                    data_done     <= 1;
                    delay_counter <= delay_counter + 1;
                end
                else begin
                    delay_counter <= 0;
                    data_done     <= 0;
                    rom_state     <= 3;
                end
            end
            3 : begin
                if (~start_sig) begin
                    rom_state <= 0;
                end
            end
            default : begin
                rom_state <= 0;
            end
        endcase
    end
    
endmodule
